Design of 4 Bit Rotate Left Network at Low Power and Small Delay Using MOS Transistor at 45 nm Channel Length

Author(s)

Surajit Bari, Debashis De, Angsuman Sarkar

Author affiliation

1ECE Department, Narula Institute of Technology, Agarpara, Kolkata, India
2 Department of CSE, Maulana Abul Kalam Azad University of Technology, West Bengal, Salt Lake, BF-142, Kolkata, India 
3ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, India

Abstract

In this work the design of 4 bit rotate left network with Metal Oxide Semiconductor (MOS) transistor having channel of 45nm has been presented. To report average power consumption and delay of the network the magnitude of the voltage of control signals and signal sources has been diverse from 0.5 V to 1.2 V .The measured value of average power consumption is 19μW and gate delay is 17.3ps at on voltage of 1 volt. The overall circuit has been simulated using Tanner SPICE (T-SPICE) software.

Keywords

rotate left, nano, power, delay, T-SPICE