Analytical Surface Potential Based Modeling of Drain Current & Trans-Conductance of Work Function Engineered Gate Recessed S/D SOI/SON MOSFET

Author(s)

Tiya Dey Malakar, Partha Bhattacharyya, Subir Kr. Sarkar

Author affiliation

 1 Department of Electronics & Communication Engineering,Kolkata, 700015, India 
2 Department of Electronics & TeleCommunication Engineering, IIEST,Howrah,  711103, India 
3 Department of Electronics & TeleCommunication Engineering, Jadavpur University, 700075, India

Abstract

In this paper analytical surface potential model based drain current model for work function Engineered Gate (WFEG) Recessed S/D SOI/SON MOSFET has been presented. The 2 D Poisson’s equation for surface potential in the channel region with appropriate boundary condition can be solved which in turn determine the threshold voltage of the recessed S/D structure. Incorporating the channel length modulation, effective mobility and modified threshold voltage, the drain current has been calculated. Since it has already been established that WFEG structure is better than the single Gate and Dual Material Gate MOSFETs, the results of our recessed structures are compared with the results of conventional WFEG SOI/SON MOSFET. The analytical results are also compared with the results of 2D device simulator to validate our present model. The results verified that Recessed Structure is superior over conventional WFEG SOI/SON MOSFET structure due to its higher current driving capability and enhance transconductance which is the figure of merit of the device.

Keywords

Work function engineered gate (WFEG); recessed S/D