Author(s):
Surajit Bari^1a, , Debashis De^2b, Angsuman Sarkar^3c

Author Affiliation:
¹ECE Department, Narula Institute of Technology, Agarpara, Kolkata, India
²Department of CSE, Maulana Abul Kalam Azad University of Technology, West Bengal, Salt Lake, BF-142, Kolkata, India
³ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

In this work the design of 4 bit rotate left network with Metal Oxide Semiconductor (MOS) transistor having channel of 45nm has been presented. To report average power consumption and delay of the network the magnitude of the voltage of control signals and signal sources has been diverse from 0.5 V to 1.2 V .The measured value of average power consumption is 19μW and gate delay is 17.3ps at on voltage of 1 volt. The overall circuit has been simulated using Tanner SPICE (T-SPICE) software.

KEYWORDS:
rotate left, nano, power, delay, T-SPICE