An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET

Author(s)

Payel Pandit, Rahul Das, Shramana Chakraborty, Arpan Dasgupta, Atanu Kundu, Chandan K. Sarkar

Author affiliation

1Department of Electronics and Communication Engineering, Heritage Institute of Technology, Kolkata 700107, India
2Nano Device Simulation Laboratory, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India

Abstract

In this paper the characteristics of 14 nm Underlap Double Gate (U-DG) NMOSFET with gate stack (GS) with different underlap length are studied. Underlap optimization is the key solution to minimize short channel effects, such as Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL).The underlap length has been optimized based on the on current to off current ratio (ION/IOFF). The RF performance comparison for the devices with 4 nm, 6 nm and 8 nm underlap length is shown in terms of the parameters such as total gate capacitance (Cgg), intrinsic capacitances (Cgs ,Cgd), intrinsic resistances(Rgs , Rgd), transport delay (τm), the unity current gain cut-off frequency (fT) and the maximum frequency of oscillation( fmax).

Keywords

Underlap; gatestack; RF analysis; cut-off frequency