7-Segment Decoder in Near Threshold Regime for Ultra Low Power Application

Author(s)

Sandipta Mal, Akash Mondal, Anindita Podder, Anirban Chowdhury

Author affiliation

Advanced VLSI Design Lab, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata, India

Abstract

Energy and power are the two most primary design parameters. Over the last few decades, we observed a steady increase in the count of transistors on a chip conforming Moore’s law leading to advancement in various computing accomplishments. But the largest hindrance to this flourishing growth is related to energy and power consumption and thus finding energy-efficient solutions is very much crucial for the sustenance of the semiconductor industry. Therefore, the aim of the designers in this era is to overcome the challenge of energy efficient computing and make performances free from the realms of power through voltage scaling techniques. Till now voltage scaling techniques have proved to be very effective but with subthreshold design representing the ultimatum of voltage scaling. However, subthreshold design has certain major performance penalties. This paper defines and explores design space called the near-threshold region. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics.

Keywords

Near-threshold; 7-segment display; CMOS