Asymmetric Junctionless Double Gate (JLDG) Silicon on Nothing (SON) MOSFET Modified with the Concept of Work Function Engineering: A Comparative Performance Study
Priyanka Saha, Dinesh Kumar Dash, Subhramita Basak, Subir Kumar Sarkar
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India
An analytical compact model for asymmetric junctionless double gate silicon-on-nothing (JLDG SON) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is developed here. This model is developed based on the solution of 2D Poisson’s equation considering different dielectric medium, dielectric thickness of both front and back gates in addition to different applied gate voltages. This model is then further extended to develop a modified structure incorporating work function engineering with linearly graded binary metal alloy gate electrode to further suppress SCEs. Our analytical results found to be in good agreement with simulation results, thereby fulfilling the accuracy of the present analytical model.
Junctionless; double gate; silicon on nothing (SON); threshold voltage roll-off; drain induced barrier lowering; subthreshold swing, work function engineeringY,Government of India.