ASYMMETRIC JUNCTIONLESS DOUBLE GATE (JLDG) SILICON ON NOTHING (SON) MOSFET MODIFIED WITH THE CONCEPT OF WORK FUNCTION ENGINEERING: A COMPARATIVE PERFORMANCE STUDY

Author(s):
Priyanka Saha1, Dinesh Kumar Dash2, Subhramita Basak3, Subir Kumar Sarkar4

Doi: 10.7508/aiem.01.2017.17.21

Author Affiliation:
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

Abstract

An analytical compact model for asymmetric junctionless double gate silicon-on-nothing (JLDG SON) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is developed here. This model is developed based on the solution of 2D Poisson’s equation considering different dielectric medium, dielectric thickness of both front and back gates in addition to different applied gate voltages. This model is then further extended to develop a modified structure incorporating work function engineering with linearly graded binary metal alloy gate electrode to further suppress SCEs. Our analytical results found to be in good agreement with simulation results, thereby fulfilling the accuracy of the present analytical model.

KEYWORDS:
Junctionless; double gate; silicon on nothing (SON); threshold voltage roll-off; drain induced barrier lowering; subthreshold swing, work function engineeringY,Government of India.