Author(s):
Payel Pandit¹, Rahul Das¹, Shramana Chakraborty¹, Arpan Dasgupta¹, Atanu Kundu¹, Chandan K. Sarkar²

Doi: 10.7508/aiem.01.2017.06.10

Author Affiliation:
¹Department of Electronics and Communication Engineering, Heritage Institute of Technology, Kolkata 700107, India
²Nano Device Simulation Laboratory, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

In this paper the characteristics of 14 nm Underlap Double Gate (U-DG) NMOSFET with gate stack (GS) with different underlap length are studied. Underlap optimization is the key solution to minimize short channel effects, such as Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL).The underlap length has been optimized based on the on current to off current ratio (ION/IOFF). The RF performance comparison for the devices with 4 nm, 6 nm and 8 nm underlap length is shown in terms of the parameters such as total gate capacitance (Cgg), intrinsic capacitances (Cgs ,Cgd), intrinsic resistances(Rgs , Rgd), transport delay (τm), the unity current gain cut-off frequency (fT) and the maximum frequency of oscillation( fmax).

KEYWORDS:
Underlap; gatestack; RF analysis; cut-off frequency