High Speed Reconfigurable ALU Design for Radix (2^n±m)
Arindam Banerjee, Swapan Bhattacharyya, Arpan Deyasi
Department of ECE, JISCE, Kalyani, West Bengal, India
Department of ECE, RCCIIT, Kolkata, West Bengal, India
High speed ALU design for (2^n±m) radix has been reported in this paper. The design has been achieved using the contemporary reconfigurable logic. Here n and m are any positive integer. So far the arithmetic circuit design is concerned; all the architectures have been shown in binary, ternary or quaternary logic. Here we have shown that the conventional logical operations like AND, OR, XOR etc. can be designed in any radix system. Our design follows a generic structure which can be implemented in any radix system. In the proposed design scheme ten arithmetic operations have been incorporated. The design has been verified using Xilinx ISE and implemented using Vertex-7 FPGA.
ALU; radix; residue; FPGA; reconfigurable logic