Author(s):
Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder

Author Affiliation:
Advanced VLSI Design Lab, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

The growing pace and complexity of today’s outlines imply a noteworthy rise in the power consumption of very-large-scale integration (VLSI) chips. We all are passionate to give the steadiness in the curve of power consumption day by day. To encounter this problem, researchers have evolved many different design approaches to minimize power. As electronic components are being blended into small, portable gadgets, the requirement increases for growing functionality, with chopped size and slighter power consumption in unit time. This suggests a requirement to stabilize ultra-low power with area-efficient design. In this paper, we explore the implementation of 1-bit full adder using 4:1 Multiplexer in sub-threshold region for ultra-low-power applications in both CMOS logic and ECRL logic. The results of the simulations show that the ECRL logics have some advantages compared to their CMOS logic counterparts of same circuit. Enhancing the execution of these circuits will guide to improvement of gross system performance.

KEYWORDS:
Full Adder; Multiplexer; Sub-Threshold; CMOS; ECRL; Ultra Low Power