Design and Average Power Consumption Analysis of 3-Stage CMOS Ring Oscillator Circuit at 32 nm Channel Length
Surajit Bari*, Arunima Maity, Debashis De, Angsuman Sarkar
ECE Department, Narula Institute of Technology, Agarpara, Kolkata, India
Department of CSE, Maulana Abul Kalam Azad University of Technology, West Bengal, Salt Lake, BF-142, Kolkata, India
ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, India
This work represents the design of a 3-Stage Complementary Metal Oxide Semiconductor (CMOS) ring oscillator circuit at 32 nm channel length of MOS (metal oxide semiconductor) transistor. In order to report average power consumption across the ring oscillator circuit, power supply voltage VDD has been varied keeping other parameters as fixed quantity. The value of VDD is supposed to vary from 0.5 V to 1.2 V. The circuit has been simulated using Tanner SPICE (T-SPICE) tools. It is observed from the simulation results that as VDD is decreasing average power consumption across the circuit also decreasing .This indicates that for low power design the value of VDD needs to be reduced .The average power consumption across the CMOS ring oscillator circuit at 1 V of VDD is 67.2 μW. The simulation results for average power consumption are satisfactory context to recent low power Integrated Circuit (IC) design and fabrication.
Ring oscillator; CMOS; IC; low power; T-SPICE