Average Power Consumption and Delay Analysis of Schmitt Trigger Circuit using Low Dimensional MOS Transistor
Surajit Bari, Arunima Maity, Debashis De, Angsuman Sarkar
ECE Department, Narula Institute of Technology, Agarpara, Kolkata, India
Department of CSE, Maulana Abul Kalam Azad University of Technology, West Bengal,Salt Lake, BF-142, Kolkata, India
ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, India
In this work the average power consumption analysis of Schmitt trigger circuit using Metal Oxide Semiconductor (MOS) transistor having channel length of 70 nm has been reported. It is found that the average power consumption is 3.3 μW at power supply voltage (VDD) of 1V. The gate delay is one of the key parameter to analyze the speed of response of the Schmitt trigger circuit. In order to investigate the gate delay power supply voltage VDD has been varied from 0.5 V to 1.2 V. From the simulation results it is seen that gate delay of the Schmitt trigger circuit at 1 V VDD is 24 ps. The order of power consumption and gate delay for the Schmitt trigger circuit in this work is satisfactory and the values are relevant to recent low power and high speed Integrated Circuit (IC) design. It has also been observed form simulation results that as VDD is decreasing power consumption across Schmitt trigger circuit decreases however gate delay increases. This indicates for low power and high speed Schmitt trigger circuit design value of VDD needs to be optimized. Tanner SPICE (T-SPICE) tools have been used to design the Schmitt trigger circuit, to report its average power consumption and gate delay.
Schmitt trigger; IC; nano; power; delay; T-SPICE