A Robust Design Optimization Technique for the Low Power CMOS VLSI
Kalyani Government Engineering College, Electrical Engineering Department, Kalyani, West Bengal, PIN-741235, India
The paper depicts on the design optimization skills for the low power CMOS VLSI for the reliable and robust power supply entity to encourage the compactness, faster computation, power loss reductions, uncharacteristic leakages and reduction of the parasitic effects for the wider substitute of the applications. The design textures of the VLSI devices not only strengthen low power consumptions in terms of the power transfer proficiency, dynamic power, static power and the low power designing but also operate in the stable sector inside the solid integrated circuit (IC) as faster software simulation, modeling, commercial success and considerable cost effective solutions.
CMOS VLSI; power consumption; modeling; analysis; computational speed and results.