Design and Implementaion of Energy Efficient 88 Multiplier using Single Phase Adiabatic Dynamic Logic


Manash Chanda, Tanushree Ganguli, Rounak Dutta, Shouvik Mukhopadhyay, Swapnadip De

Author affiliation

Advanced VLSI Design Lab, Dept.of ECE, Meghnad Saha Institute of Technology, Kolkata 700150, India


This paper represents the design and implementation of 8×8 adiabatic multiplier using Quasi-Static Single-phase Adiabatic Dynamic Logic (SPADL). SPADL uses only a single sinusoidal supply-clock to for the minimal control circuitry and less power overheads. Simplicity and static logic resembled characteristics of SPADL substantially decreases circuit complexity with improved driving ability and circuit robustness in case of proposed structures. In order to provide insights into difference between the proposed logic and previously reported multiphase logics, 8-bit carry look-ahead adder and multipliers are implemented in TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL consumes only 61.32% and 51.11% of total energy of the Clocked Adiabatic Logic (CAL) for clock frequencies ranging from 1 MHz to 100 MHz frequency, in case of 8-bit CLA and 8×8 multiplier. SPADL based 8-bit CLA and 8×8 multiplier also save more than 85% energy than the CMOS counterpart at 100 MHz frequency. High energy efficiency of SPADL makes it suitable for implementing performance efficient VLSI circuitry.


Adiabatic; energy efficiency; single phase; quasi static; 8×8 Multiplier