Effect of Gate Length Downscaling on RF/Analog and Linearity Performance of a Junctionless Double Gate MOSFET for Analog/Mixed Signal System-On-Chip Applications & It’s Comparative Study with Conventi
Biswajit Baral, Sudhansu Mohan Biswal, Jagruti Padhee, Debashis De, Angsuman Sarkar
Silicon Institute of Technology, Bhubaneswar, India
West Bengal University of Technology, Kolkata, India
Kalyani Government Engg. College, Kolkata, India
The linearity and RF Performance of a Junctionless Double Gate MOSFET (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOS have shown great promise for high performance digital application due to its superior short channel effect performance and ease of fabrication. In analog and RF circuit application, linearity testing and RF performance is an important issue which arises due to non linear behavior of the devices. In this paper, different figure of merits for linearity and RF/Analog performance parameters like Transconductance (gm), Intrinsic Gain (gmRout), Transconductance Generation Factor (gm/ID), Cut off frequency (fT ), Maximum frequency of oscillation (fmax), Gain Bandwidth Product (GBW), Variable Intercept Point of Second order (VIP2), 1-dB compression are analyzed. The effect of gate length down scaling on these performance parameters has also been carried out. The results reveal that down scaled JL DGMOS shows great promise to become a competitive contender for Analog/Mixed signal System On Chip (SOC) application by demonstrating a significant improvement in its RF performance with gate length downscaling.
Transconductance(gm); intrinsic gain; transconductance generation factor; cut off frequency (ft); maximum frequency of oscillation (fmax); gain bandwidth product (GBW); variable intercept point of second order (VIP2); 1-dB compression