Effect of Gate Dielectrics on Simulated Device Characteristics of Nanoscale Double Gate Heterostructure MOSFET

Author(s)

Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar

Author affiliation

ECE Department, MCKV Institute of Engineering, Liluah, Howrah, India
ECE Department, Kalyani Government Engineering College, Kalyani, WB, India
ETCE Department, Nano Device Simulation Laboratory, Jadavpur University, India

Abstract

This paper presents the simulation results of a double gate hetersostructure MOSFET by 2D device simulator, with effective channel length down to 12 nm. A detailed investigation of the impact of gate dielectric material on different Analog and RF performance of an InGaAs/InP heterostructure DG MOSFET is carried out. A thorough analysis of the key figure-of-merits such as transconductance (gm), cutoff frequency (fT), maximum frequency of oscillation (fmax), VIP2 and VIP3 are performed for various dielectric materials with dielectric constant varying from 3.9 to 22. Numerical device simulation data, obtained using 2D device simulator: ATLAS, were compared for different gate dielectrics.

Keywords

III-V MOSFET; heterostructure; double gate, dielectric material