Author(s):
Gollamudi Sai Sivaram^1a, Shramana Chakraborty^1b, Rahul Das^1c, Arpan Dasgupta^1d, Atanu Kundu^1e, Chandan K. Sarkar^2f

Author Affiliation:
¹Department of Electronics and Communication Engineering, Heritage Institute of Technology, Kolkata 700107, India
²Nano Device Simulation Laboratory, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

This paper presents a systematic comparative study of analog performances of an underlapped double gate (U-DG) NMOSFETs with Gate Stack (GS) with varying underlap length. In highly scaled devices, conventionally, symmetric underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE’s). However, this leads to increased channel resistance decreasing the ON current. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies with underlap being present only at the source side. Different parameters such as drain characteristics, transfer characteristics, transconductance (gm), transconductance generating factor (gm/Id) and output resistance (ro) have been analyzed for various underlap lengths. For optimization of the desired underlap length, the DIBL and the Ion/ Ioff ratio have been considered. Analysis suggested that the device with underlap length of 23 nm shows superior analog performance in terms of better Ion/Ioff ratio and better resistance to SCE’s. Thus, the optimal underlap length is 23 nm.

KEYWORDS:
Gate stack; asymmetric underlap; analog performance; DG NMOSFETs