AREA EFFICIENT LOW POWER SCAN FLIP-FLOP DESIGN BASED ON QUANTUM-DOT CELLULAR AUTOMATA
Jadav Chandra Das1a, Bikash Debnath1b, Debashis De1,2c
1Department of Computer Science and Engineering, West Bengal University of Technology, India
2Department of Physics, University of Western Australia, Perth, Australia
This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited
Minute digital circuit at nanoscale can be designed using Quantum-Dot Cellular Automata (QCA). Due to inherent nature, QCA circuits have low power dissipation and can perform faster switching during operations. This work illustrates a new QCA based design of 2:1 multiplexer and D flip-flop. Farther those designs are used to achieve an optimized circuit for scan flip-flop. The designs are claimed optimized after comparing with existing ones in the start of the art. Design accuracy is confirmed with theoretical values. The estimation of power dissipation is achieved, which shows the circuits have low power dissipation. The designs can be used to as a building block to achieve low power general purpose nano-processor.
QCA; majority gate; multiplexer; D flip-flop; scan flip-flop; power dissipation.