Author(s):
Sudhansu Mohan Biswal^1a, Biswajit Baral^1b, Debashis De^2c, Angsuman Sarkar^3d

Author Affiliation:
¹ECE Department, Silicon Institute of Technology, Bhubaneswar, Odisha, India
²West Bengal University of Technology, Kolkata, India
³Kalyani Government Engineering College, Kolkata, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

In this paper, we present a simulation study to report the effect of gate-length downscaling on the analog/RF performance and Linearity investigation of Si-based DG Tunnel FET (TFET). The different RF/analog figure-of-merits such as gm, RO, intrinsic gain, fT, fmax and GBW and 1-dB Compression point considered as important linearity matrices of a TFET are extracted and the influence of gate-length downscaling on these parameters is analyzed. Results reveals that superior RF and Linearity performance was obtained with gate-length downscaling. However, these advantages diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates a trade-off between the analog and RF performance of a down-scaled Si-based TFET. This paper concludes that Si-based TFETs have enormous potential to be a promising contender to the conventional bulk MOSFETs for realization of future generation low-power analog/RF applications.

KEYWORDS:
Tunnel FET; transconductance; transconductance generation factor; cut-off frequency; maximum frequency of oscillation; gain bandwidth product; TCAD; 1-dB compression point