Author(s):
Manash Chanda^a, Tanushree Ganguli^b, Rounak Dutta^c, Shouvik Mukhopadhya^d, Swapnadip De^e

Author Affiliation:
Advanced VLSI Design Lab, Dept.of ECE, Meghnad Saha Institute of Technology, Kolkata, India

This is an open access article distributed under the Creative Commons Attribution License CC BY 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

Design and analysis of 8 transistor full adder using 3T XOR gate has been implemented in this paper. The proposed design style has achieved comparatively higher noise margin and speed than the existing structures. Silicon area can be reduced significantly by reducing the transistor count of the adder circuits. Power, speed and the power delay product of the 3T XOR and the 8T full adder are detailed in depth. The CADENCE simulation results based on 90nm process technology indicate that the proposed 8T adder and XOR achieved up to 37% and 51% improvement in speed compared to the existing ones.

KEYWORDS:
Low power; 3T XOR; 8T-Full adder; high speed; area efficient